1. Field of the Invention
This invention relates to the field of built-in self test modules for integrated circuits, and more particularly, to a system and method for reconfiguring built-in self test modules to provide adjustable tests for integrated memories.
2. Description of the Related Art
It is common practice for the manufacturers of application specific integrated circuit (ASIC) chips to test the functionality of the ASIC chips at the manufacturing site. After the chips have been tested and certified for shipment, the users generally depend on the reliability of the chips for their own system design. As the density and complexity of ASIC chips increases, this reliability becomes more difficult to attain. Before the ASIC chips are released for shipment, they typically undergo testing to verify the functionality of the chip. This is necessary because it is not uncommon for a significant percentage of ASIC chips to fail due to manufacturing defects and degradation faults.
In the past, ASIC chips have been tested using external Automatic Test Equipment (ATE) at the manufacturing site. Since speed is an issue, and since it is often difficult to provide external access to certain chip functionality, an increasingly standard technique is the use of built-in self-test (BIST) circuitry. In this technique, additional hardware is added to a design so that testing is accomplished with a reduced need for external special purpose testing hardware. One popular example of BIST circuitry is the use of a pseudorandom vector generator and a data compactor. The generator produces the test vectors to be applied to a circuit under test and the compactor reduces the response to these vectors to a single value (e.g., 16 or 32 bits) known as the signature. It is then possible for the ATE to initialize or provide parameters to the generator and examine signatures from the compactor to verify the functionality of the chip.
Random Access Memory (RAM), Read-Only Memory (ROM), and multipliers are common test targets, but they may be deeply embedded within the IC logic making them difficult to access for test purposes. BIST circuitry may be fabricated on the integrated circuit itself to verify the functionality of these devices. The BIST logic generates input test patterns for the RAMs, ROMs, or multipliers and determines if the output data agrees with expected values. The output data from the sub circuits can either be compared with the expected data from the BIST directly or compacted in a signature register. The BIST logic typically generates a failure signal upon detecting a device fault.
While BIST circuitry can verify device functionality, it typically does not provide any assistance in determining the cause of any detected failure. While customizing the BIST circuitry to perform this function is certainly possible, it is expected that this would result in excessive cost and complexity being added to the integrated circuit. Nevertheless, it would be desirable to have a method for debugging embedded devices which leverages off of the existing BIST circuitry to minimize added cost and complexity.